Development of High-k Gates for Advances CMOS Devices

Development of High-k Gates for Advances CMOS Devices High dielectric constant (high-k) materials, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), alumina (Al2O3), and their silicates, have drawn a great deal of attention in recent years for potential use as gate dielectrics in advanced CMOS processes [1]. With high dielectric constants, gate dieletrics can be made thicker than SiO2 while achieving the same capacitance. The result is leakage current that can be lower by as much as several orders of magnitude. However, there are still technical challenges to overcome, such as Vt instability [2-4], carrier channel mobility degradation [5-9], and long-term device reliability [10-13]. One of the important issues preventing implementation of high-k gates is the trapping of charges in the pre-existing traps inside these dielectrics [14-15]. When the transistor is turned on, some of the channel carriers will be accumulated in the gate dielectric due to the vertical electrical field, resulting in a shift of threshold voltage and a reduction in drain current. Fully understanding charge-trapping and these related mechanisms is the key to understanding channel mobility degradation and device reliability problems. However, traditional DC testing techniques may not accurately characterize these mechanisms.